This past semester (Fall 2025), I had the opportunity to take ECE 427: Advanced VLSI Design (formerly known as https://courses.grainger.illinois.edu/ECE498HK/fa2024/index.html).

We basically get 1mm^2 of silicon (on TSMC’s 65nm node) to tape out whatever we want. I wanted to share my experience and ramble on about the things me and my teammates did.

The Grand Idea

Timeline

RTL, Synthesis and Simulation

EDA Tools

Handoff and Wrapup